1. Field of the Invention
The present invention relates generally to a circuit design, and more particularly to an equalizer circuit design.
2. Description of the Prior Art
Electrical pulses transmitted on a band-limited signaling path disperse in time as they travel from source to destination. In systems in which data is transmitted as a sequence of level-encoded electrical pulses, such time-domain dispersion results in a blending of neighboring pulses; an effect known as dispersion-type inter-symbol interference (ISI). Dispersion-type ISI becomes more pronounced at faster signaling rates, ultimately degrading the signal quality to the point at which distinctions between originally transmitted signal levels may be lost.
FIG. 1 illustrates a block diagram for RX Decision Feedback Equalization (DFE). DFE is a non-linear equalizer. The slicer makes a symbol decision, i.e. quantizes input, and ISI is then directly subtracted from the incoming signal via a feedback FIR filter. Filter tap coefficients can be adaptively tuned without any back-channel.
FIG. 2 is a conventional block diagram of a loop-unrolled DFE in which two parallel paths are used to pre-compute the resultant product of the first tap of the FBE for both possible outcomes (i.e., a logical one or a logical zero) of the decision device. The first parallel path of loop-unrolling device, which includes the slicer, presupposes that the next decided value output from decision device, corresponding to the bit received prior to the bit being currently processed in the incoming serial data stream, will be a logical one value. The slicer receives the output of a combiner to combine the tap weights, H2, H3, H4, H5, and a threshold level H1. However, the second parallel path presupposes that the next decided value output from decision device, corresponding to the bit received prior to the bit being currently processed in the incoming serial data stream, will be a logical one value. The slicer receives the output of a combiner to combine the tap weights, H2, H3, H4, H5, and a threshold level −H1.
Once the decision device determines the next decided symbol value at its output; the decided symbol value can be used as the select input to multiplexer. Thus, the output of the parallel path in the loop-unrolling device that corresponds to the actual symbol value output by decision device is selected. Loop-unrolling device thereby eliminates the critical path containing the next decided symbol value.
FIG. 3 illustrates a conventional comparator with a DAC-selectable threshold in US patent publication No. 20120213267. The comparator 400 includes a preamplifier 401 and a sampling circuit 425. The preamplifier 401 includes a pair of differential amplifiers 402 and 403 each biased by a respective current DAC (IDAC) 411 and 413, and each has first and second output nodes 418 and 419 coupled to a supply voltage via a respective resistive element, R. The resistive elements may be implemented, for example, using diode-configured transistors, biased transistors, resistors, or any other active or passive circuitry for establishing a resistance. Transistors 405 and 404 within differential amplifier 402 have widths W1 and W2, respectively, with W1 being greater than W2. A differential input signal composed of signal components D and /D is coupled to each of the differential amplifiers 402, 403 such that D is coupled to transistors 404 and 408 and /D is coupled to transistors 405 and 407. Thus, if D is greater than /D, transistors 404 and 408 will collectively sink more current than transistors 405 and 407, thereby causing the voltage on output node 418 to be pulled down (i.e., via the resistive element, R, coupled to the output node 418) more than the voltage on output node 419.
The conventional threshold voltage design needs to track with the parameters of the transistors such as Vgs-Vth (voltage between the gate and the source voltage-threshold voltage of the MOSFET transistor) or the dimension of the channel in the MOSFET transistors.
Therefore, what is needed is a new way to design a threshold voltage generator in a DFE circuit to track with less parameters.